Recent advances in semiconductor processing have made possible the sale and manufacture of "semi-custom" integrated circuits, particularly ASICs (Application Specific Integrated Circuits) based on gate arrays and standard cell designs. These ASICs are generally produced in relatively low volumes according to a user's specification which makes use of a manufacturer's standard cell or gate array building blocks. ASICs offer the user a relatively quick, cost-effective approach to meeting the needs of a rapidly changing electronics marketplace.
ASICs have grown sufficiently in complexity, however, that 10,000 gate designs are commonplace, and 100,000 gate ASICs are not unheard of. Along with this complexity has come a need for more sophisticated semiconductor packages. These high-gate-count ASICs often require hundreds of pins, and can have very demanding power supply pin requirements. These requirement have been dealt with in the prior art, but usually by providing some form of a custom designed package.
Custom-designed packages often make use of multi-layer ceramic package technology, whereby a semiconductor die (the ASIC die in this case) is mounted in a "sandwich" of ceramic "circuit boards", with pins or other connection points on at least one surface, which accomplish whatever bond-finger routing and/or power supply pin/plane layout is necessary to meet the user's needs (the internal leads o traces which connect (route) the external connection points of the package to a semiconductor die mounted therein are commonly referred to as "bond-fingers"). These non-standard packages can be very costly, however, and may require time and effort which is incompatible with the rapid-turnaround ASIC production environment, thereby costing the user both time and money.
Lower-cost "standard" packages include both ceramic devices and plastic devices. While plastic devices are not typically "sandwiched" into multi-layer "circuit boards" in quite the same fashion as ceramic packages, it is known in the prior art to provide plastic packages with several embedded layers of patterned conductive traces to accomplish effectively the same result.
Another factor complicating the ASIC marketplace is that users often want the same ASIC packaged in several different packages, for example, one package in a PLCC (plastic leaded chip carrier, a plastic package with `J` shaped leads folded underneath on four sides of the package) format, another in a PQFP (plastic quad flat pack, a plastic package with leads extending out in a planar configuration from four sides of the package), and yet another in a PGA (Pin Grid Array, package with an array of pins on a bottom surface) or BGA (Bump Grid Array, similar to PGA, but with reflowable solder bumps instead of pins).
One simple response to the power-supply pin problem is to use a standard package and simply connect power supplies to a number of different pins. A problem with this approach is that high-speed designs require power supply "planes" within the package, and the standard "bond-fingers" to which ordinary pins are connected do not provide equivalent performance to a power supply plane.
In response to these needs, U.S. Pat. No. 4,972,253, entitled "PROGRAMMABLE CERAMIC HIGH PERFORMANCE CUSTOM PACKAGE", issued on Nov. 20, 1990 to Palino and Fisher, discloses a "programmable" multi-layer ceramic semiconductor package wherein all layers are standardized except for a "via layer" which is provides user-specific signal routing. This layer is produced prior to assembly of the package. The final package is then assembled with the customized via layer, which can connect pins to signals on the semiconductor die or to power supply connections on the semiconductor die via a power plane arrangement. Using this approach, it is possible to visualize an inventory of standard devices awaiting customization with a special "via layer". This programmable package offers significant advantages over the prior-art technique of developing full custom packages for each customer, but it still requires custom design of one layer and custom assembly, both of which require a specialized facility, design tools, and manufacturing equipment.
Another problem with this type of programmable package is that in order to properly anticipate all of the users' needs, it may be necessary to provide a number of power planes in excess of those which would ordinarily be necessary, increasing the complexity and cost of the package.
Evidently, then, there is a need for a standard package with programmable configuration, which can be customized using tools commonly available to ASIC users.